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VHDL: What is correct way to model open collector output for FPGA?

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VHDL: What is correct way to model open collector output for FPGA?

Multiplexing an I2C bus between two masters on a Xilinx FPGAHow to wire output buses togetherI2C communication with AVR - how to let the lines “float”?I2C SCL ground issueHow SPI and I2C latch data?I2C ACK bit glitchWhy do I2C lines use open drain driver instead of tri-state drivers?Multiple VHDL testbench for Single entity1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSimHow to verify a VHDL I2C master?

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4

$begingroup$

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?


2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

fpga vhdl i2c testbench

share|improve this question

asked 9 hours ago

quantum231quantum231

4,0341563125

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  intel.com/content/www/us/en/programmable/support/…
  $endgroup$
  – Eugene Sh.
  9 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  The main difficulty is simulation side of this
  $endgroup$
  – quantum231
  1 hour ago
  

  
  
  
  

add a comment | 

4

$begingroup$

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?


2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

fpga vhdl i2c testbench

share|improve this question

asked 9 hours ago

quantum231quantum231

4,0341563125

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  intel.com/content/www/us/en/programmable/support/…
  $endgroup$
  – Eugene Sh.
  9 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  The main difficulty is simulation side of this
  $endgroup$
  – quantum231
  1 hour ago
  

  
  
  
  

add a comment | 

$begingroup$

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?


2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

fpga vhdl i2c testbench

share|improve this question

asked 9 hours ago

quantum231quantum231

4,0341563125

$endgroup$

share|improve this question

asked 9 hours ago

quantum231quantum231

4,0341563125

share|improve this question

asked 9 hours ago

quantum231quantum231

4,0341563125

asked 9 hours ago

quantum231quantum231

4,0341563125

asked 9 hours ago

quantum231quantum231

4,0341563125

2 Answers
2

active

oldest

votes

4

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered 9 hours ago

KingDukenKingDuken

1,4092617

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Why 5 lines of Verilog when you can just do assign DOUT = ENABLE ? 1'b0 : 1'bz;? (Also, your ENABLE is acting as a DISABLE, making the code a bit confusing).
  $endgroup$
  – The Photon
  7 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ThePhoton The code comes from Xilinx's website (as mentioned in my answer).
  $endgroup$
  – KingDuken
  5 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Thanks King. Here the question is solely from simulation perspective. If both transmitter and receiver are driving 'Z' onto the SDA and one of them reads in the SDA, if it is not pulled high then it shall read in 'Z'. If it is pulled high out should read '1'. The problem is, if we pull high externally using '1'then it shall clash with SDA being driven to '0' as happens with open collectors. Can we use 'H'? Don't know since never used it. If driven externally to 'H' and internally to 'Z', will reading internally give '1' or 'H'?
  $endgroup$
  – quantum231
  1 hour ago
  
  

  
  
  
  

add a comment | 

2

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered 9 hours ago

TEMLIBTEMLIB

2,0371714

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  But is 'Z' + 'H' = '1'? This is the confusing part. In other words, if both receiver and transmitter are driving 'Z' onto SDA and then one of them reads the value on SDA, it should get '1' since it is pulled high externally right?
  $endgroup$
  – quantum231
  1 hour ago
  

  
  
  
  

add a comment | 

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4

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered 9 hours ago

KingDukenKingDuken

1,4092617

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Why 5 lines of Verilog when you can just do assign DOUT = ENABLE ? 1'b0 : 1'bz;? (Also, your ENABLE is acting as a DISABLE, making the code a bit confusing).
  $endgroup$
  – The Photon
  7 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ThePhoton The code comes from Xilinx's website (as mentioned in my answer).
  $endgroup$
  – KingDuken
  5 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Thanks King. Here the question is solely from simulation perspective. If both transmitter and receiver are driving 'Z' onto the SDA and one of them reads in the SDA, if it is not pulled high then it shall read in 'Z'. If it is pulled high out should read '1'. The problem is, if we pull high externally using '1'then it shall clash with SDA being driven to '0' as happens with open collectors. Can we use 'H'? Don't know since never used it. If driven externally to 'H' and internally to 'Z', will reading internally give '1' or 'H'?
  $endgroup$
  – quantum231
  1 hour ago
  
  

  
  
  
  

add a comment | 

4

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered 9 hours ago

KingDukenKingDuken

1,4092617

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Why 5 lines of Verilog when you can just do assign DOUT = ENABLE ? 1'b0 : 1'bz;? (Also, your ENABLE is acting as a DISABLE, making the code a bit confusing).
  $endgroup$
  – The Photon
  7 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ThePhoton The code comes from Xilinx's website (as mentioned in my answer).
  $endgroup$
  – KingDuken
  5 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Thanks King. Here the question is solely from simulation perspective. If both transmitter and receiver are driving 'Z' onto the SDA and one of them reads in the SDA, if it is not pulled high then it shall read in 'Z'. If it is pulled high out should read '1'. The problem is, if we pull high externally using '1'then it shall clash with SDA being driven to '0' as happens with open collectors. Can we use 'H'? Don't know since never used it. If driven externally to 'H' and internally to 'Z', will reading internally give '1' or 'H'?
  $endgroup$
  – quantum231
  1 hour ago
  
  

  
  
  
  

add a comment | 

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered 9 hours ago

KingDukenKingDuken

1,4092617

$endgroup$

dout <= 'Z' when din='1' else '0';

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

share|improve this answer

answered 9 hours ago

KingDukenKingDuken

1,4092617

answered 9 hours ago

KingDukenKingDuken

1,4092617

answered 9 hours ago

KingDukenKingDuken

1,4092617

2

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered 9 hours ago

TEMLIBTEMLIB

2,0371714

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  But is 'Z' + 'H' = '1'? This is the confusing part. In other words, if both receiver and transmitter are driving 'Z' onto SDA and then one of them reads the value on SDA, it should get '1' since it is pulled high externally right?
  $endgroup$
  – quantum231
  1 hour ago
  

  
  
  
  

add a comment | 

2

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered 9 hours ago

TEMLIBTEMLIB

2,0371714

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  But is 'Z' + 'H' = '1'? This is the confusing part. In other words, if both receiver and transmitter are driving 'Z' onto SDA and then one of them reads the value on SDA, it should get '1' since it is pulled high externally right?
  $endgroup$
  – quantum231
  1 hour ago
  

  
  
  
  

add a comment | 

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered 9 hours ago

TEMLIBTEMLIB

2,0371714

$endgroup$

sda <= 'Z' when dout='1' else '0';

sda <='H';

share|improve this answer

answered 9 hours ago

TEMLIBTEMLIB

2,0371714

answered 9 hours ago

TEMLIBTEMLIB

2,0371714

answered 9 hours ago

TEMLIBTEMLIB

2,0371714