Mfcttrf

I'm looking into writing a little software emulator, that emulates/runs instructions.

Easiest would be to invent my own instruction set, but I thought it would be more fun if what I write an emulator for an instruction set that already has a C++/C compiler.

What is the easiest instruction set/architecture that has a (hopefully stable) C++ and/or C compiler?

With easiest I mean the least amount of instructions.

Easiest would be to invent my own instruction set

uh, ok, we might come from very different experiences here…

With easiest I mean the least amount of instructions.

That's not necessarily the easiest to implement. Often, having more instructions is a good complexity tradeoff compared to having more complex instructions.

So my question is, what is the easiest instruction set/architecture that has a (hopefully stable) C++ and/or C compiler?

This sounds like no job for C++, so let's concentrate on C. (If you don't understand the difference having C++ RAII paradigm makes, you might not be in the optimum position to design your own ISA.)

Puh, some microcontroller instruction set that is early, but not too early (because too early would imply "designed around the limitations of digital logic of that time, like e.g. 8051).

AVR might be a good choice, though I personally don't like that too much.

I hear Zilog Z80 is easy to implement (there's really several Z80 implementations out there), but it's pretty ancient, and not very comfortable (being from the mid-70s).

If you really just want a small core to control what your system is doing, why not pick one of the many processor core designs that are out there?

For example, RISC-V is a (fairly complex) instruction set architecture, with mature compilers, and many open source implementations. For a minimal FPGA core, picoRV32 would probably the core of choice. And on a computer, you'd just run QEMU.

You should take al look at the PIC microcontroller family. The instruction set is limited to 35 different instructions, while the controller is actually still used.
Look at the datasheet at page 228: PIC16F datasheet

The controller is using 8 bits and is also available with less periphery, but that does not change anything for the instruction set.

I hope for something with like 50 instructions. Also, 32 bit and c++

The "Beta" architecture used in MIT's 6.004 core track class is a 32-bit RISC design often referred to as a simplification of the DEC Alpha. It's been implemented in many ways - personally in an FPGA - and at one time there was an old version of GCC for it, though that may at this point be challenging to dig up if no one is continuing to work with it.

One example of the architecture documentation is here, the full link will be retained as which year versions of the course are published online changes from time to time and it can be worth looking at several as different information may be included: https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2009/labs/

You need a One Instruction Set Computer (OISC)

A one instruction set computer (OISC), sometimes called an ultimate
reduced instruction set computer (URISC), is an abstract machine that
uses only one instruction – obviating the need for a machine language
opcode. With a judicious choice for the single instruction
and given infinite resources, an OISC is capable of being a universal
computer in the same manner as traditional computers that have
multiple instructions. OISCs have been recommended as aids in
teaching computer architecture and have been used as
computational models in structural computing research.

Whether a compiler exists, I do not know. But I suspect some unlucky student somewhere has probably been assigned the task of writing one.