relative price of a transistor and a capacitorWhat is the main Computer Memory Addressing Mechanism for Semi-Conductor Memory?Where to add a capacitorSPICE model for DRAM transistorDifference between a memory cell and a memory chip?How CMOS transistors might be used as a capacitive sensor for biopotential?How does the PNP transistor in this IR receiver circuit work?Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of dataSpeaker works with lm386 but not transistorTransistor, resistor, capacitor circuitDischarging high voltage and capacitance capacitor?
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relative price of a transistor and a capacitor
What is the main Computer Memory Addressing Mechanism for Semi-Conductor Memory?Where to add a capacitorSPICE model for DRAM transistorDifference between a memory cell and a memory chip?How CMOS transistors might be used as a capacitive sensor for biopotential?How does the PNP transistor in this IR receiver circuit work?Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of dataSpeaker works with lm386 but not transistorTransistor, resistor, capacitor circuitDischarging high voltage and capacitance capacitor?
.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty margin-bottom:0;
$begingroup$
DRAMs achieve high memory density by storing each bit of information with one transistor and one capacitor. That got me wondering, how expensive is a capacitor relative to a transistor?
transistors capacitor
asked 7 hours ago
KevinSimKevinSim
472
$endgroup$
add a comment |
$begingroup$
DRAMs achieve high memory density by storing each bit of information with one transistor and one capacitor. That got me wondering, how expensive is a capacitor relative to a transistor?
transistors capacitor
asked 7 hours ago
KevinSimKevinSim
472
$endgroup$
$begingroup$
You can find their price here. digikey.com.au/en
$endgroup$
– Ross
7 hours ago
$begingroup$
I bought my 2N2222A's for 0.36 cents (US) each. I give them away to students, so "cheap is good." Just for a benchmark.
$endgroup$
– jonk
7 hours ago
2
$begingroup$
There is no comparison of discrete component costs to a DRAM. Consider there is a lot more to make a DRAM work than a single cell of a transistor and some femtofarad capacitor. But consider an 8GB DRAM (or 64Gb) for $50 is only $0.00000000078125 per cell
$endgroup$
– Sunnyskyguy EE75
4 hours ago
add a comment |
$begingroup$
DRAMs achieve high memory density by storing each bit of information with one transistor and one capacitor. That got me wondering, how expensive is a capacitor relative to a transistor?
transistors capacitor
asked 7 hours ago
KevinSimKevinSim
472
$endgroup$
DRAMs achieve high memory density by storing each bit of information with one transistor and one capacitor. That got me wondering, how expensive is a capacitor relative to a transistor?
transistors capacitor
transistors capacitor
asked 7 hours ago
KevinSimKevinSim
472
asked 7 hours ago
KevinSimKevinSim
472
asked 7 hours ago
KevinSimKevinSim
472
asked 7 hours ago
KevinSimKevinSim
472
asked 7 hours ago
KevinSimKevinSim
472
472
$begingroup$
You can find their price here. digikey.com.au/en
$endgroup$
– Ross
7 hours ago
$begingroup$
I bought my 2N2222A's for 0.36 cents (US) each. I give them away to students, so "cheap is good." Just for a benchmark.
$endgroup$
– jonk
7 hours ago
2
$begingroup$
There is no comparison of discrete component costs to a DRAM. Consider there is a lot more to make a DRAM work than a single cell of a transistor and some femtofarad capacitor. But consider an 8GB DRAM (or 64Gb) for $50 is only $0.00000000078125 per cell
$endgroup$
– Sunnyskyguy EE75
4 hours ago
add a comment |
$begingroup$
You can find their price here. digikey.com.au/en
$endgroup$
– Ross
7 hours ago
$begingroup$
I bought my 2N2222A's for 0.36 cents (US) each. I give them away to students, so "cheap is good." Just for a benchmark.
$endgroup$
– jonk
7 hours ago
2
$begingroup$
There is no comparison of discrete component costs to a DRAM. Consider there is a lot more to make a DRAM work than a single cell of a transistor and some femtofarad capacitor. But consider an 8GB DRAM (or 64Gb) for $50 is only $0.00000000078125 per cell
$endgroup$
– Sunnyskyguy EE75
4 hours ago
$begingroup$
You can find their price here. digikey.com.au/en
$endgroup$
– Ross
7 hours ago
$begingroup$
You can find their price here. digikey.com.au/en
$endgroup$
– Ross
7 hours ago
$begingroup$
I bought my 2N2222A's for 0.36 cents (US) each. I give them away to students, so "cheap is good." Just for a benchmark.
$endgroup$
– jonk
7 hours ago
$begingroup$
I bought my 2N2222A's for 0.36 cents (US) each. I give them away to students, so "cheap is good." Just for a benchmark.
$endgroup$
– jonk
7 hours ago
2
2
$begingroup$
There is no comparison of discrete component costs to a DRAM. Consider there is a lot more to make a DRAM work than a single cell of a transistor and some femtofarad capacitor. But consider an 8GB DRAM (or 64Gb) for $50 is only $0.00000000078125 per cell
$endgroup$
– Sunnyskyguy EE75
4 hours ago
$begingroup$
There is no comparison of discrete component costs to a DRAM. Consider there is a lot more to make a DRAM work than a single cell of a transistor and some femtofarad capacitor. But consider an 8GB DRAM (or 64Gb) for $50 is only $0.00000000078125 per cell
$endgroup$
– Sunnyskyguy EE75
4 hours ago
add a comment |
2 Answers
2
active
oldest
votes
$begingroup$
If you're asking this question from a VLSI perspective then it certainly is going to depend on the process, but it will be a complicated question to answer. It looks like a typical DRAM memory is constructed by a process that's designed to make densely packed DRAM cells, and in a modern DRAM the capacitor is built above the transistor such that they have a similar cost. A more typical CMOS process doesn't have the facility to make small area capacitors like this, and is optimized to make small transistors and no capacitors at all.
People who may have designed or used DRAM cells or a DRAM process are likely to be under NDA and unable to talk about the particulars like cell sizes.
We relate area to cost because a larger silicon chip requires more materials and more effort to produce, but also because it presents more opportunities for a defect to destroy it reducing yeilds and requiring a large portion of the production to be thrown out.
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
$endgroup$
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
2
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
add a comment |
$begingroup$
The question isn't necessarily about the relative cost of each transistor versus each capacitor. Once the masks are made for manufacturing the silicon chips, a chip made purely of transistors wouldn't cost any more than a chip made of purely capacitors (Excepting the number of steps in the manufacturing process, which a mixed chip would need all steps anyway).
The difference comes in the real estate on the silicon. The simplest way to store a single bit in SRAM (Using purely transistors) requires 6 transistors, and is made this way: 
Image pulled from the SRAM wikipedia page.
Alternatively, we can use a DRAM cell. As you mentioned, DRAM uses one transistor and one capacitor, which means we can fit many more of these two-component storage cells onto a single chip than the six-component storage cells. DRAM is cheaper because it can be made significantly more dense than SRAM, not because of the relative cost of the transistors and capacitors on the silicon chip.
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
$endgroup$
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
If you're asking this question from a VLSI perspective then it certainly is going to depend on the process, but it will be a complicated question to answer. It looks like a typical DRAM memory is constructed by a process that's designed to make densely packed DRAM cells, and in a modern DRAM the capacitor is built above the transistor such that they have a similar cost. A more typical CMOS process doesn't have the facility to make small area capacitors like this, and is optimized to make small transistors and no capacitors at all.
People who may have designed or used DRAM cells or a DRAM process are likely to be under NDA and unable to talk about the particulars like cell sizes.
We relate area to cost because a larger silicon chip requires more materials and more effort to produce, but also because it presents more opportunities for a defect to destroy it reducing yeilds and requiring a large portion of the production to be thrown out.
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
$endgroup$
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
2
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
add a comment |
$begingroup$
If you're asking this question from a VLSI perspective then it certainly is going to depend on the process, but it will be a complicated question to answer. It looks like a typical DRAM memory is constructed by a process that's designed to make densely packed DRAM cells, and in a modern DRAM the capacitor is built above the transistor such that they have a similar cost. A more typical CMOS process doesn't have the facility to make small area capacitors like this, and is optimized to make small transistors and no capacitors at all.
People who may have designed or used DRAM cells or a DRAM process are likely to be under NDA and unable to talk about the particulars like cell sizes.
We relate area to cost because a larger silicon chip requires more materials and more effort to produce, but also because it presents more opportunities for a defect to destroy it reducing yeilds and requiring a large portion of the production to be thrown out.
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
$endgroup$
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
2
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
add a comment |
$begingroup$
If you're asking this question from a VLSI perspective then it certainly is going to depend on the process, but it will be a complicated question to answer. It looks like a typical DRAM memory is constructed by a process that's designed to make densely packed DRAM cells, and in a modern DRAM the capacitor is built above the transistor such that they have a similar cost. A more typical CMOS process doesn't have the facility to make small area capacitors like this, and is optimized to make small transistors and no capacitors at all.
People who may have designed or used DRAM cells or a DRAM process are likely to be under NDA and unable to talk about the particulars like cell sizes.
We relate area to cost because a larger silicon chip requires more materials and more effort to produce, but also because it presents more opportunities for a defect to destroy it reducing yeilds and requiring a large portion of the production to be thrown out.
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
$endgroup$
If you're asking this question from a VLSI perspective then it certainly is going to depend on the process, but it will be a complicated question to answer. It looks like a typical DRAM memory is constructed by a process that's designed to make densely packed DRAM cells, and in a modern DRAM the capacitor is built above the transistor such that they have a similar cost. A more typical CMOS process doesn't have the facility to make small area capacitors like this, and is optimized to make small transistors and no capacitors at all.
People who may have designed or used DRAM cells or a DRAM process are likely to be under NDA and unable to talk about the particulars like cell sizes.
We relate area to cost because a larger silicon chip requires more materials and more effort to produce, but also because it presents more opportunities for a defect to destroy it reducing yeilds and requiring a large portion of the production to be thrown out.
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
answered 7 hours ago
Andrew MacraeAndrew Macrae
744114
744114
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
2
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
add a comment |
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
2
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
$begingroup$
Standard CMOS has various resistors: gate_poly, wells, Nactive, Pactive, etc. And various capacitors are available, with varying linearity and absorption-coefficients: gate_bulk is a cap; drain_bulk is a cap, Metal1 to Metal2 is a cap, etc.
$endgroup$
– analogsystemsrf
5 hours ago
2
2
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
$begingroup$
@analogsystemsrf DRAM processes are not standard CMOS processes. The capacitance needed for a DRAM cell is much more than the parasitic capacitances you mention.
$endgroup$
– Elliot Alderson
5 hours ago
add a comment |
$begingroup$
The question isn't necessarily about the relative cost of each transistor versus each capacitor. Once the masks are made for manufacturing the silicon chips, a chip made purely of transistors wouldn't cost any more than a chip made of purely capacitors (Excepting the number of steps in the manufacturing process, which a mixed chip would need all steps anyway).
The difference comes in the real estate on the silicon. The simplest way to store a single bit in SRAM (Using purely transistors) requires 6 transistors, and is made this way:
Image pulled from the SRAM wikipedia page.
Alternatively, we can use a DRAM cell. As you mentioned, DRAM uses one transistor and one capacitor, which means we can fit many more of these two-component storage cells onto a single chip than the six-component storage cells. DRAM is cheaper because it can be made significantly more dense than SRAM, not because of the relative cost of the transistors and capacitors on the silicon chip.
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
$endgroup$
add a comment |
$begingroup$
The question isn't necessarily about the relative cost of each transistor versus each capacitor. Once the masks are made for manufacturing the silicon chips, a chip made purely of transistors wouldn't cost any more than a chip made of purely capacitors (Excepting the number of steps in the manufacturing process, which a mixed chip would need all steps anyway).
The difference comes in the real estate on the silicon. The simplest way to store a single bit in SRAM (Using purely transistors) requires 6 transistors, and is made this way:
Image pulled from the SRAM wikipedia page.
Alternatively, we can use a DRAM cell. As you mentioned, DRAM uses one transistor and one capacitor, which means we can fit many more of these two-component storage cells onto a single chip than the six-component storage cells. DRAM is cheaper because it can be made significantly more dense than SRAM, not because of the relative cost of the transistors and capacitors on the silicon chip.
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
$endgroup$
add a comment |
$begingroup$
The question isn't necessarily about the relative cost of each transistor versus each capacitor. Once the masks are made for manufacturing the silicon chips, a chip made purely of transistors wouldn't cost any more than a chip made of purely capacitors (Excepting the number of steps in the manufacturing process, which a mixed chip would need all steps anyway).
The difference comes in the real estate on the silicon. The simplest way to store a single bit in SRAM (Using purely transistors) requires 6 transistors, and is made this way:
Image pulled from the SRAM wikipedia page.
Alternatively, we can use a DRAM cell. As you mentioned, DRAM uses one transistor and one capacitor, which means we can fit many more of these two-component storage cells onto a single chip than the six-component storage cells. DRAM is cheaper because it can be made significantly more dense than SRAM, not because of the relative cost of the transistors and capacitors on the silicon chip.
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
$endgroup$
The question isn't necessarily about the relative cost of each transistor versus each capacitor. Once the masks are made for manufacturing the silicon chips, a chip made purely of transistors wouldn't cost any more than a chip made of purely capacitors (Excepting the number of steps in the manufacturing process, which a mixed chip would need all steps anyway).
The difference comes in the real estate on the silicon. The simplest way to store a single bit in SRAM (Using purely transistors) requires 6 transistors, and is made this way:
Image pulled from the SRAM wikipedia page.
Alternatively, we can use a DRAM cell. As you mentioned, DRAM uses one transistor and one capacitor, which means we can fit many more of these two-component storage cells onto a single chip than the six-component storage cells. DRAM is cheaper because it can be made significantly more dense than SRAM, not because of the relative cost of the transistors and capacitors on the silicon chip.
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
answered 7 hours ago
ambitiose_sed_ineptumambitiose_sed_ineptum
53729
53729
add a comment |
add a comment |
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$begingroup$
You can find their price here. digikey.com.au/en
$endgroup$
– Ross
7 hours ago
$begingroup$
I bought my 2N2222A's for 0.36 cents (US) each. I give them away to students, so "cheap is good." Just for a benchmark.
$endgroup$
– jonk
7 hours ago
2
$begingroup$
There is no comparison of discrete component costs to a DRAM. Consider there is a lot more to make a DRAM work than a single cell of a transistor and some femtofarad capacitor. But consider an 8GB DRAM (or 64Gb) for $50 is only $0.00000000078125 per cell
$endgroup$
– Sunnyskyguy EE75
4 hours ago