Detect the first rising edge of 3 input signalsUnclocked, edge-triggered version of RS flip-flop?Difference between rising edge falling edge D flip flop (asynchronous reset)?Rising edge pulse detector from logic gatesCombining 8 digital signalsconvert falling / rising edge to pulses with minimal componentsPRESET and CLEAR in a D Flip FlopDigital circuit to toggle on rising edge of two signalsdigital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edgegates operation in flip flopAsynchronous SET DFF but except rising edge of CLK
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Detect the first rising edge of 3 input signals
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Detect the first rising edge of 3 input signals
Unclocked, edge-triggered version of RS flip-flop?Difference between rising edge falling edge D flip flop (asynchronous reset)?Rising edge pulse detector from logic gatesCombining 8 digital signalsconvert falling / rising edge to pulses with minimal componentsPRESET and CLEAR in a D Flip FlopDigital circuit to toggle on rising edge of two signalsdigital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edgegates operation in flip flopAsynchronous SET DFF but except rising edge of CLK
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$begingroup$
I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected.
Is there a digital circuit from logic gates, flip flop that can do that?
I am thinking about flip flop but the problem is that it detects with every rising edge not just the first rising edge.
digital-logic logic-gates flipflop synthesis
asked 3 hours ago
anhnhaanhnha
54611247
$endgroup$
|
show 1 more comment
$begingroup$
I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected.
Is there a digital circuit from logic gates, flip flop that can do that?
I am thinking about flip flop but the problem is that it detects with every rising edge not just the first rising edge.
digital-logic logic-gates flipflop synthesis
asked 3 hours ago
anhnhaanhnha
54611247
$endgroup$
1
$begingroup$
And when does out go low?
$endgroup$
– Tyler
2 hours ago
$begingroup$
You need a combination of Flip-Flops and logic gates.
$endgroup$
– Mattman944
2 hours ago
$begingroup$
Are you trying to detect if y and z go high before the second rising edge on x? Or, if they went high after the second rising edge, would that also result in the output going high?
$endgroup$
– Annie
2 hours ago
$begingroup$
@Tyler it will remain high from that time
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Annie: no, the order doesn't matter, only detect the first rising edges of 3 inputs. After the first rising edges of 3 inputs are detected, the output goes high and remains at that value
$endgroup$
– anhnha
1 hour ago
|
show 1 more comment
$begingroup$
I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected.
Is there a digital circuit from logic gates, flip flop that can do that?
I am thinking about flip flop but the problem is that it detects with every rising edge not just the first rising edge.
digital-logic logic-gates flipflop synthesis
asked 3 hours ago
anhnhaanhnha
54611247
$endgroup$
I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected.
Is there a digital circuit from logic gates, flip flop that can do that?
I am thinking about flip flop but the problem is that it detects with every rising edge not just the first rising edge.
digital-logic logic-gates flipflop synthesis
digital-logic logic-gates flipflop synthesis
asked 3 hours ago
anhnhaanhnha
54611247
asked 3 hours ago
anhnhaanhnha
54611247
asked 3 hours ago
anhnhaanhnha
54611247
asked 3 hours ago
anhnhaanhnha
54611247
asked 3 hours ago
anhnhaanhnha
54611247
54611247
1
$begingroup$
And when does out go low?
$endgroup$
– Tyler
2 hours ago
$begingroup$
You need a combination of Flip-Flops and logic gates.
$endgroup$
– Mattman944
2 hours ago
$begingroup$
Are you trying to detect if y and z go high before the second rising edge on x? Or, if they went high after the second rising edge, would that also result in the output going high?
$endgroup$
– Annie
2 hours ago
$begingroup$
@Tyler it will remain high from that time
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Annie: no, the order doesn't matter, only detect the first rising edges of 3 inputs. After the first rising edges of 3 inputs are detected, the output goes high and remains at that value
$endgroup$
– anhnha
1 hour ago
|
show 1 more comment
1
$begingroup$
And when does out go low?
$endgroup$
– Tyler
2 hours ago
$begingroup$
You need a combination of Flip-Flops and logic gates.
$endgroup$
– Mattman944
2 hours ago
$begingroup$
Are you trying to detect if y and z go high before the second rising edge on x? Or, if they went high after the second rising edge, would that also result in the output going high?
$endgroup$
– Annie
2 hours ago
$begingroup$
@Tyler it will remain high from that time
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Annie: no, the order doesn't matter, only detect the first rising edges of 3 inputs. After the first rising edges of 3 inputs are detected, the output goes high and remains at that value
$endgroup$
– anhnha
1 hour ago
1
1
$begingroup$
And when does out go low?
$endgroup$
– Tyler
2 hours ago
$begingroup$
And when does out go low?
$endgroup$
– Tyler
2 hours ago
$begingroup$
You need a combination of Flip-Flops and logic gates.
$endgroup$
– Mattman944
2 hours ago
$begingroup$
You need a combination of Flip-Flops and logic gates.
$endgroup$
– Mattman944
2 hours ago
$begingroup$
Are you trying to detect if y and z go high before the second rising edge on x? Or, if they went high after the second rising edge, would that also result in the output going high?
$endgroup$
– Annie
2 hours ago
$begingroup$
Are you trying to detect if y and z go high before the second rising edge on x? Or, if they went high after the second rising edge, would that also result in the output going high?
$endgroup$
– Annie
2 hours ago
$begingroup$
@Tyler it will remain high from that time
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Tyler it will remain high from that time
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Annie: no, the order doesn't matter, only detect the first rising edges of 3 inputs. After the first rising edges of 3 inputs are detected, the output goes high and remains at that value
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Annie: no, the order doesn't matter, only detect the first rising edges of 3 inputs. After the first rising edges of 3 inputs are detected, the output goes high and remains at that value
$endgroup$
– anhnha
1 hour ago
|
show 1 more comment
3 Answers
3
active
oldest
votes
$begingroup$
You could use the circuit below with 3 D flip-flops and one 3-input AND gate.
You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the schematic).
simulate this circuit – Schematic created using CircuitLab
answered 35 mins ago
joribamajoribama
4366
$endgroup$
add a comment |
$begingroup$
Put each input on the set of an SR latch, and AND all the outputs together.
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
$endgroup$
add a comment |
$begingroup$
As defined 3 rising edges are asynchronous thus reset 3 latches and
NOR input= output
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
$endgroup$
add a comment |
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3 Answers
3
active
oldest
votes
3 Answers
3
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
You could use the circuit below with 3 D flip-flops and one 3-input AND gate.
You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the schematic).
simulate this circuit – Schematic created using CircuitLab
answered 35 mins ago
joribamajoribama
4366
$endgroup$
add a comment |
$begingroup$
You could use the circuit below with 3 D flip-flops and one 3-input AND gate.
You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the schematic).
simulate this circuit – Schematic created using CircuitLab
answered 35 mins ago
joribamajoribama
4366
$endgroup$
add a comment |
$begingroup$
You could use the circuit below with 3 D flip-flops and one 3-input AND gate.
You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the schematic).
simulate this circuit – Schematic created using CircuitLab
answered 35 mins ago
joribamajoribama
4366
$endgroup$
You could use the circuit below with 3 D flip-flops and one 3-input AND gate.
You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the schematic).
simulate this circuit – Schematic created using CircuitLab
answered 35 mins ago
joribamajoribama
4366
answered 35 mins ago
joribamajoribama
4366
answered 35 mins ago
joribamajoribama
4366
answered 35 mins ago
joribamajoribama
4366
4366
add a comment |
add a comment |
$begingroup$
Put each input on the set of an SR latch, and AND all the outputs together.
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
$endgroup$
add a comment |
$begingroup$
Put each input on the set of an SR latch, and AND all the outputs together.
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
$endgroup$
add a comment |
$begingroup$
Put each input on the set of an SR latch, and AND all the outputs together.
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
$endgroup$
Put each input on the set of an SR latch, and AND all the outputs together.
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
answered 2 hours ago
Scott SeidmanScott Seidman
22.8k43287
22.8k43287
add a comment |
add a comment |
$begingroup$
As defined 3 rising edges are asynchronous thus reset 3 latches and
NOR input= output
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
$endgroup$
add a comment |
$begingroup$
As defined 3 rising edges are asynchronous thus reset 3 latches and
NOR input= output
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
$endgroup$
add a comment |
$begingroup$
As defined 3 rising edges are asynchronous thus reset 3 latches and
NOR input= output
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
$endgroup$
As defined 3 rising edges are asynchronous thus reset 3 latches and
NOR input= output
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
answered 1 hour ago
Sunnyskyguy EE75Sunnyskyguy EE75
73.3k228103
73.3k228103
add a comment |
add a comment |
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1
$begingroup$
And when does out go low?
$endgroup$
– Tyler
2 hours ago
$begingroup$
You need a combination of Flip-Flops and logic gates.
$endgroup$
– Mattman944
2 hours ago
$begingroup$
Are you trying to detect if y and z go high before the second rising edge on x? Or, if they went high after the second rising edge, would that also result in the output going high?
$endgroup$
– Annie
2 hours ago
$begingroup$
@Tyler it will remain high from that time
$endgroup$
– anhnha
1 hour ago
$begingroup$
@Annie: no, the order doesn't matter, only detect the first rising edges of 3 inputs. After the first rising edges of 3 inputs are detected, the output goes high and remains at that value
$endgroup$
– anhnha
1 hour ago