How does the Z80 determine which peripheral sent an interrupt? The Next CEO of Stack OverflowWhy does the Z80 have a half-carry bit?How fast is memcpy on the Z80?How can a C64 interrupt let the KERNAL keep operating?Which Z80 opcodes can I use without a stack?Why does the Z80 include the RLD and RRD instructions?Intel 8080 and Altair 8800. 256 I/0 ports, but only 7 free RST (interrupt subroutine) - how it works?Is it possible to switch the interrupt source of the C64 to VIC without changing the IRQ routine?Why do we need to acknowledge the interrupt from VIC-II?How do I Interface a PS/2 Keyboard without Modern Techniques?Where does the Z80 processor start executing from?
Can I run my washing machine drain line into a condensate pump so it drains better?
Which kind of appliances can one connect to electric sockets located in a airplane's toilet?
Can I equip Skullclamp on a creature I am sacrificing?
Is "for causing autism in X" grammatical?
Are there any unintended negative consequences to allowing PCs to gain multiple levels at once in a short milestone-XP game?
MessageLevel in QGIS3
Preparing Indesign booklet with .psd graphics for print
Real integral using residue theorem - why doesn't this work?
sp_blitzCache results Memory grants
Why is the US ranked as #45 in Press Freedom ratings, despite its extremely permissive free speech laws?
What exact does MIB represent in SNMP? How is it different from OID?
What does "Its cash flow is deeply negative" mean?
How to invert MapIndexed on a ragged structure? How to construct a tree from rules?
Is it my responsibility to learn a new technology in my own time my employer wants to implement?
What's the best way to handle refactoring a big file?
Unreliable Magic - Is it worth it?
Complex fractions
Calculus II Question
To not tell, not take, and not want
Why do airplanes bank sharply to the right after air-to-air refueling?
If Nick Fury and Coulson already knew about aliens (Kree and Skrull) why did they wait until Thor's appearance to start making weapons?
Elegant way to replace substring in a regex with optional groups in Python?
Why do professional authors make "consistency" mistakes? And how to avoid them?
If the heap is initialized for security, then why is the stack uninitialized?
How does the Z80 determine which peripheral sent an interrupt?
The Next CEO of Stack OverflowWhy does the Z80 have a half-carry bit?How fast is memcpy on the Z80?How can a C64 interrupt let the KERNAL keep operating?Which Z80 opcodes can I use without a stack?Why does the Z80 include the RLD and RRD instructions?Intel 8080 and Altair 8800. 256 I/0 ports, but only 7 free RST (interrupt subroutine) - how it works?Is it possible to switch the interrupt source of the C64 to VIC without changing the IRQ routine?Why do we need to acknowledge the interrupt from VIC-II?How do I Interface a PS/2 Keyboard without Modern Techniques?Where does the Z80 processor start executing from?
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 5 hours ago
Jacob GarbyJacob Garby
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
edited 5 hours ago
Jacob Garby
asked 5 hours ago
Jacob GarbyJacob Garby
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 5 hours ago
Jacob GarbyJacob Garby
2206
asked 5 hours ago
Jacob GarbyJacob Garby
2206
2206
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
add a comment |
1 Answer
1
active
oldest
votes
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
add a comment |
Your Answer
StackExchange.ready(function()
var channelOptions =
tags: "".split(" "),
id: "648"
;
initTagRenderer("".split(" "), "".split(" "), channelOptions);
StackExchange.using("externalEditor", function()
// Have to fire editor after snippets, if snippets enabled
if (StackExchange.settings.snippets.snippetsEnabled)
StackExchange.using("snippets", function()
createEditor();
);
else
createEditor();
);
function createEditor()
StackExchange.prepareEditor(
heartbeatType: 'answer',
autoActivateHeartbeat: false,
convertImagesToLinks: false,
noModals: true,
showLowRepImageUploadWarning: true,
reputationToPostImages: null,
bindNavPrevention: true,
postfix: "",
imageUploader:
brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
allowUrls: true
,
noCode: true, onDemand: true,
discardSelector: ".discard-answer"
,immediatelyShowMarkdownHelp:true
);
);
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
StackExchange.ready(
function ()
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fretrocomputing.stackexchange.com%2fquestions%2f9475%2fhow-does-the-z80-determine-which-peripheral-sent-an-interrupt%23new-answer', 'question_page');
);
Post as a guest
Required, but never shown
1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
add a comment |
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
add a comment |
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
answered 4 hours ago
RaffzahnRaffzahn
54.4k6133219
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
add a comment |
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
3 hours ago
add a comment |
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Thanks for contributing an answer to Retrocomputing Stack Exchange!
- Please be sure to answer the question. Provide details and share your research!
But avoid …
- Asking for help, clarification, or responding to other answers.
- Making statements based on opinion; back them up with references or personal experience.
To learn more, see our tips on writing great answers.
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
StackExchange.ready(
function ()
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fretrocomputing.stackexchange.com%2fquestions%2f9475%2fhow-does-the-z80-determine-which-peripheral-sent-an-interrupt%23new-answer', 'question_page');
);
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
