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Why does Intel's Haswell chip allow multiplication to be twice as fast as addition?

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1

$begingroup$

I was reading this very interesting question on SO:

https://stackoverflow.com/questions/21819682/is-integer-multiplication-really-same-speed-as-addition-on-modern-cpu

One of the comments said:

"It's worth nothing that on Haswell, the FP multiply throughput is
double that of FP add. That's because both ports 0 and 1 can be used
for multiply, but only port 1 can be used for addition. That said, you
can cheat with fused-multiply adds since both ports can do them."

Why is it that they would allow twice as much simultaneous multiplication compared to addition?

I'm new to EE stack exchange, so please excuse me if this is more appropriate for a different SE. It is more of a "hardware engineering" question than a general electrical engineering question, but certainly not a "software" question for SO or SU.

parallel hardware port intel calculator

share|improve this question

asked 8 hours ago

user1271772user1271772

10622 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  I suspect floating point multiplication might just take less die area.
  $endgroup$
  – DKNguyen
  7 hours ago
  
  

  
  
  
  


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  1
  

  
  
  
  
  
  

  
  $begingroup$
  Thank you @DKNguyen! But multiplication involves way more electronics than addition (in fact addition is the final step of multiplication, so whatever circuitry needed for multiplication will also include whatever is needed for addition), so I don't see how it can take up less die area!
  $endgroup$
  – user1271772
  7 hours ago
  

  
  
  
  


• 
  
  
  

  
  1
  

  
  
  
  
  
  

  
  $begingroup$
  Yes, it's the correct place to ask. You should add a "computer-architecture" tag to your question.
  $endgroup$
  – 比尔盖子
  6 hours ago
  

  
  
  
  


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  1
  

  
  
  
  
  
  

  
  $begingroup$
  FP multiplication is addition. See logarithms.
  $endgroup$
  – Janka
  6 hours ago
  

  
  
  
  

add a comment | 

1

$begingroup$

I was reading this very interesting question on SO:

https://stackoverflow.com/questions/21819682/is-integer-multiplication-really-same-speed-as-addition-on-modern-cpu

One of the comments said:

"It's worth nothing that on Haswell, the FP multiply throughput is
double that of FP add. That's because both ports 0 and 1 can be used
for multiply, but only port 1 can be used for addition. That said, you
can cheat with fused-multiply adds since both ports can do them."

Why is it that they would allow twice as much simultaneous multiplication compared to addition?

I'm new to EE stack exchange, so please excuse me if this is more appropriate for a different SE. It is more of a "hardware engineering" question than a general electrical engineering question, but certainly not a "software" question for SO or SU.

parallel hardware port intel calculator

share|improve this question

asked 8 hours ago

user1271772user1271772

10622 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  I suspect floating point multiplication might just take less die area.
  $endgroup$
  – DKNguyen
  7 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  1
  

  
  
  
  
  
  

  
  $begingroup$
  Thank you @DKNguyen! But multiplication involves way more electronics than addition (in fact addition is the final step of multiplication, so whatever circuitry needed for multiplication will also include whatever is needed for addition), so I don't see how it can take up less die area!
  $endgroup$
  – user1271772
  7 hours ago
  

  
  
  
  


• 
  
  
  

  
  1
  

  
  
  
  
  
  

  
  $begingroup$
  Yes, it's the correct place to ask. You should add a "computer-architecture" tag to your question.
  $endgroup$
  – 比尔盖子
  6 hours ago
  

  
  
  
  


• 
  
  
  

  
  1
  

  
  
  
  
  
  

  
  $begingroup$
  FP multiplication is addition. See logarithms.
  $endgroup$
  – Janka
  6 hours ago
  

  
  
  
  

add a comment | 

$begingroup$

I was reading this very interesting question on SO:

https://stackoverflow.com/questions/21819682/is-integer-multiplication-really-same-speed-as-addition-on-modern-cpu

One of the comments said:

"It's worth nothing that on Haswell, the FP multiply throughput is
double that of FP add. That's because both ports 0 and 1 can be used
for multiply, but only port 1 can be used for addition. That said, you
can cheat with fused-multiply adds since both ports can do them."

Why is it that they would allow twice as much simultaneous multiplication compared to addition?

I'm new to EE stack exchange, so please excuse me if this is more appropriate for a different SE. It is more of a "hardware engineering" question than a general electrical engineering question, but certainly not a "software" question for SO or SU.

parallel hardware port intel calculator

share|improve this question

asked 8 hours ago

user1271772user1271772

10622 bronze badges

$endgroup$

share|improve this question

asked 8 hours ago

user1271772user1271772

10622 bronze badges

share|improve this question

asked 8 hours ago

user1271772user1271772

10622 bronze badges

asked 8 hours ago

user1271772user1271772

10622 bronze badges

asked 8 hours ago

user1271772user1271772

10622 bronze badges

1 Answer
1

active

oldest

votes

6

$begingroup$

This possibly answers the title of the question, if not the body:

Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two exponents), potentially requiring a large variable amount of shift before the adder. Then renormalizing the result of the mantissa addition might be needed, potentially requiring another large variable amount of shift in order to properly format the floating point result. The two mantissa barrel shifters thus potentially require more gate delays, greater wire delays, or extra cycles that exceed the delay of a well compacted carry-save-adder-tree multiplier front end.

share|improve this answer

edited 4 hours ago

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  This is all very abstruse to me and seems quite esoteric. I have a PhD in Applied Mathematics and 10 years of post-PhD experience and yet had to look up "mantissa". What you're saying sounds like addition is more expensive than multiplication, but everywhere else I look, multiplication takes more clock cycles of latency time than addition. There's more to do in multiplication than addition, in fact multiplication involves an addition at the end, so all those "gate delays", "wire delays" and "extra cycles" that you say addition requires, should also be required for the last step of multiplying!
  $endgroup$
  – user1271772
  3 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @user1271772, integer multiplication certainly takes more resources (either time or gates) than integer addition. For floating point, everything is much more complicated. If you haven't heard the term mantissa you haven't gone very far in studying floating point computing.
  $endgroup$
  – The Photon
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @user1271772, for a basic overview of modern (since 1990ish) floating point representation, google "what every computer scientist should know about floating point arithmetic".
  $endgroup$
  – The Photon
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Read up on the works of William Kahan, who was a professor in both the Mathematics and EECS departments when I was at UC Berkeley.
  $endgroup$
  – hotpaw2
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @The Photon: I came across that article in my first year of grad school more than 10 years ago, and I remember the title being very catchy, but I didn't read it. You are right that I haven't gone very far in studying floating point computing, I just use it a lot.
  $endgroup$
  – user1271772
  1 hour ago
  

  
  
  
  

 | 
show 1 more comment

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6

$begingroup$

This possibly answers the title of the question, if not the body:

Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two exponents), potentially requiring a large variable amount of shift before the adder. Then renormalizing the result of the mantissa addition might be needed, potentially requiring another large variable amount of shift in order to properly format the floating point result. The two mantissa barrel shifters thus potentially require more gate delays, greater wire delays, or extra cycles that exceed the delay of a well compacted carry-save-adder-tree multiplier front end.

share|improve this answer

edited 4 hours ago

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  This is all very abstruse to me and seems quite esoteric. I have a PhD in Applied Mathematics and 10 years of post-PhD experience and yet had to look up "mantissa". What you're saying sounds like addition is more expensive than multiplication, but everywhere else I look, multiplication takes more clock cycles of latency time than addition. There's more to do in multiplication than addition, in fact multiplication involves an addition at the end, so all those "gate delays", "wire delays" and "extra cycles" that you say addition requires, should also be required for the last step of multiplying!
  $endgroup$
  – user1271772
  3 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @user1271772, integer multiplication certainly takes more resources (either time or gates) than integer addition. For floating point, everything is much more complicated. If you haven't heard the term mantissa you haven't gone very far in studying floating point computing.
  $endgroup$
  – The Photon
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @user1271772, for a basic overview of modern (since 1990ish) floating point representation, google "what every computer scientist should know about floating point arithmetic".
  $endgroup$
  – The Photon
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Read up on the works of William Kahan, who was a professor in both the Mathematics and EECS departments when I was at UC Berkeley.
  $endgroup$
  – hotpaw2
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @The Photon: I came across that article in my first year of grad school more than 10 years ago, and I remember the title being very catchy, but I didn't read it. You are right that I haven't gone very far in studying floating point computing, I just use it a lot.
  $endgroup$
  – user1271772
  1 hour ago
  

  
  
  
  

 | 
show 1 more comment

6

$begingroup$

This possibly answers the title of the question, if not the body:

Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two exponents), potentially requiring a large variable amount of shift before the adder. Then renormalizing the result of the mantissa addition might be needed, potentially requiring another large variable amount of shift in order to properly format the floating point result. The two mantissa barrel shifters thus potentially require more gate delays, greater wire delays, or extra cycles that exceed the delay of a well compacted carry-save-adder-tree multiplier front end.

share|improve this answer

edited 4 hours ago

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  This is all very abstruse to me and seems quite esoteric. I have a PhD in Applied Mathematics and 10 years of post-PhD experience and yet had to look up "mantissa". What you're saying sounds like addition is more expensive than multiplication, but everywhere else I look, multiplication takes more clock cycles of latency time than addition. There's more to do in multiplication than addition, in fact multiplication involves an addition at the end, so all those "gate delays", "wire delays" and "extra cycles" that you say addition requires, should also be required for the last step of multiplying!
  $endgroup$
  – user1271772
  3 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @user1271772, integer multiplication certainly takes more resources (either time or gates) than integer addition. For floating point, everything is much more complicated. If you haven't heard the term mantissa you haven't gone very far in studying floating point computing.
  $endgroup$
  – The Photon
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @user1271772, for a basic overview of modern (since 1990ish) floating point representation, google "what every computer scientist should know about floating point arithmetic".
  $endgroup$
  – The Photon
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Read up on the works of William Kahan, who was a professor in both the Mathematics and EECS departments when I was at UC Berkeley.
  $endgroup$
  – hotpaw2
  2 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @The Photon: I came across that article in my first year of grad school more than 10 years ago, and I remember the title being very catchy, but I didn't read it. You are right that I haven't gone very far in studying floating point computing, I just use it a lot.
  $endgroup$
  – user1271772
  1 hour ago
  

  
  
  
  

 | 
show 1 more comment

$begingroup$

This possibly answers the title of the question, if not the body:

Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two exponents), potentially requiring a large variable amount of shift before the adder. Then renormalizing the result of the mantissa addition might be needed, potentially requiring another large variable amount of shift in order to properly format the floating point result. The two mantissa barrel shifters thus potentially require more gate delays, greater wire delays, or extra cycles that exceed the delay of a well compacted carry-save-adder-tree multiplier front end.

share|improve this answer

edited 4 hours ago

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges

$endgroup$

share|improve this answer

edited 4 hours ago

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges

answered 7 hours ago

hotpaw2hotpaw2

96022 gold badges1616 silver badges2727 bronze badges