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ADC first transition at 1/2 LSB - is that not a non-linearity?

Implications of INL on the accuracy and resolution of an ADCSTM32 F4 - ADC in Dual Mode SimultaneouslyStuck codes in samples from ADCOptimal tradeoff between ADC bit depth and sampling rateIntegral non linearity in ADCADC quantization - LSB random?ADC Input Stage LinearityMCP3201 ADC timing clarificationsAm I using ARM 7 LPC21xx ADC register correctly?Unwanted constant offset in ADC reading

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2

$begingroup$

[From Analog Devices Data Converter Handbook]

I understand why they chose to place the first transition at the 1/2 LSB point but does that not cause non-linearity?, since you basically have reduced the probability that a 000 code could occur?

adc

share|improve this question

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Think back to junior high geometry, y=mx+b. What you are describing, if you want to argue it is even a flaw at all (which is dubious) is at most change in b, or the offset. Still linear. Non-linearity would only occur if the spacing between the transitions points were unequal.
  $endgroup$
  – Chris Stratton
  8 hours ago
  
  

  
  
  
  


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  $begingroup$
  Okay, maybe that was a bad explanation. It is linear but is it not at a flaw? For an analog input range of 0 to 1/2LSB, the ADC produces 000. But from 1/2 LSB to 3/2 LSB, the ADC produces 001?
  $endgroup$
  – AlfroJang80
  8 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ChrisStratton Is that not the case though? The first transition region occurs at 1/2LSB and the second transition region occurs at 3/2LSB. Third transition region occurs at 2.5 LSB. Actually that is a 1 LSB difference each time. I just can't understand by looking at the graph how that's okay. The 000 digital code has a smaller analog input than the other codes. Doesn't sit well within my head.
  $endgroup$
  – AlfroJang80
  7 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  This ADC sample is single ended, if you extend the graph to negative you will see that each value is valid/represented with exactly 1lsb wide equivalent analog range (-0.5 to 0.5 lsb in this case) . This graph is cut at v>0
  $endgroup$
  – crasic
  5 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Additionally, even in single ended regime. Your application should not be really care to resolve such difference between 0/1lsb. The effective noise free bits are always less than the total number of bits, and are not related to linearity spec at all. Code words with difference of 1 lsb are redundant in a complicated manner due to noise anyway and this minor aberation should do nothing. Note that for an 8bit ADC 1 lsb is 0.25% for a 24 bit ADC it is approx 30 part per billion, equivalent to -150db. Oh boy
  $endgroup$
  – crasic
  5 hours ago
  
  

  
  
  
  

add a comment
 | 

2

$begingroup$

[From Analog Devices Data Converter Handbook]

I understand why they chose to place the first transition at the 1/2 LSB point but does that not cause non-linearity?, since you basically have reduced the probability that a 000 code could occur?

adc

share|improve this question

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Think back to junior high geometry, y=mx+b. What you are describing, if you want to argue it is even a flaw at all (which is dubious) is at most change in b, or the offset. Still linear. Non-linearity would only occur if the spacing between the transitions points were unequal.
  $endgroup$
  – Chris Stratton
  8 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Okay, maybe that was a bad explanation. It is linear but is it not at a flaw? For an analog input range of 0 to 1/2LSB, the ADC produces 000. But from 1/2 LSB to 3/2 LSB, the ADC produces 001?
  $endgroup$
  – AlfroJang80
  8 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ChrisStratton Is that not the case though? The first transition region occurs at 1/2LSB and the second transition region occurs at 3/2LSB. Third transition region occurs at 2.5 LSB. Actually that is a 1 LSB difference each time. I just can't understand by looking at the graph how that's okay. The 000 digital code has a smaller analog input than the other codes. Doesn't sit well within my head.
  $endgroup$
  – AlfroJang80
  7 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  This ADC sample is single ended, if you extend the graph to negative you will see that each value is valid/represented with exactly 1lsb wide equivalent analog range (-0.5 to 0.5 lsb in this case) . This graph is cut at v>0
  $endgroup$
  – crasic
  5 hours ago
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Additionally, even in single ended regime. Your application should not be really care to resolve such difference between 0/1lsb. The effective noise free bits are always less than the total number of bits, and are not related to linearity spec at all. Code words with difference of 1 lsb are redundant in a complicated manner due to noise anyway and this minor aberation should do nothing. Note that for an 8bit ADC 1 lsb is 0.25% for a 24 bit ADC it is approx 30 part per billion, equivalent to -150db. Oh boy
  $endgroup$
  – crasic
  5 hours ago
  
  

  
  
  
  

add a comment
 | 

$begingroup$

[From Analog Devices Data Converter Handbook]

I understand why they chose to place the first transition at the 1/2 LSB point but does that not cause non-linearity?, since you basically have reduced the probability that a 000 code could occur?

adc

share|improve this question

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

$endgroup$

share|improve this question

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

share|improve this question

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

asked 8 hours ago

AlfroJang80AlfroJang80

87066 silver badges1616 bronze badges

2 Answers
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6

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Unlike the LSB code, which can only have certain discrete values, the analog input is a real, physical, continuous voltage input, which can go above full scale and below zero (even if that violates existing table or abs max rating). What’s misleading is that the graph makes it look like the analog input range for code 0 is smaller than the others, when in fact it is the same size. It’s just that the left half of the code 0 input voltage range is below zero volts, so it is not show on this graph. If they extended the horizontal axis to include negative input voltage, it would be a straight line extending through the “missing” half of the nominal code 0 range, and continuing at 0 as the lower saturation limit, just like the full scale limit does. When you look at a bipolar ADC transfer function, it’s more obvious because the 0 voltage 0 LSB code point is in the center, with positive and negative full scale staircases in opposite directions. This unipolar ADC transfer function graph just looks weird because of where they stopped the horizontal axis.

share|improve this answer

answered 6 hours ago

MarkUMarkU

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0

$begingroup$

A typical ADC gets very, very nonlinear as you hit the saturation. The 1/2 LSB is just the tip of it, since it reads 0 for any voltage below 0. It’s all kind of theoretical anyway since most ADCs have more than 1/2 LSB of offset voltage.

share|improve this answer

answered 2 hours ago

Spehro PefhanySpehro Pefhany

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6

$begingroup$

Unlike the LSB code, which can only have certain discrete values, the analog input is a real, physical, continuous voltage input, which can go above full scale and below zero (even if that violates existing table or abs max rating). What’s misleading is that the graph makes it look like the analog input range for code 0 is smaller than the others, when in fact it is the same size. It’s just that the left half of the code 0 input voltage range is below zero volts, so it is not show on this graph. If they extended the horizontal axis to include negative input voltage, it would be a straight line extending through the “missing” half of the nominal code 0 range, and continuing at 0 as the lower saturation limit, just like the full scale limit does. When you look at a bipolar ADC transfer function, it’s more obvious because the 0 voltage 0 LSB code point is in the center, with positive and negative full scale staircases in opposite directions. This unipolar ADC transfer function graph just looks weird because of where they stopped the horizontal axis.

share|improve this answer

answered 6 hours ago

MarkUMarkU

7,54411 gold badge1313 silver badges2424 bronze badges

$endgroup$

add a comment
 | 

6

$begingroup$

Unlike the LSB code, which can only have certain discrete values, the analog input is a real, physical, continuous voltage input, which can go above full scale and below zero (even if that violates existing table or abs max rating). What’s misleading is that the graph makes it look like the analog input range for code 0 is smaller than the others, when in fact it is the same size. It’s just that the left half of the code 0 input voltage range is below zero volts, so it is not show on this graph. If they extended the horizontal axis to include negative input voltage, it would be a straight line extending through the “missing” half of the nominal code 0 range, and continuing at 0 as the lower saturation limit, just like the full scale limit does. When you look at a bipolar ADC transfer function, it’s more obvious because the 0 voltage 0 LSB code point is in the center, with positive and negative full scale staircases in opposite directions. This unipolar ADC transfer function graph just looks weird because of where they stopped the horizontal axis.

share|improve this answer

answered 6 hours ago

MarkUMarkU

7,54411 gold badge1313 silver badges2424 bronze badges

$endgroup$

add a comment
 | 

$begingroup$

Unlike the LSB code, which can only have certain discrete values, the analog input is a real, physical, continuous voltage input, which can go above full scale and below zero (even if that violates existing table or abs max rating). What’s misleading is that the graph makes it look like the analog input range for code 0 is smaller than the others, when in fact it is the same size. It’s just that the left half of the code 0 input voltage range is below zero volts, so it is not show on this graph. If they extended the horizontal axis to include negative input voltage, it would be a straight line extending through the “missing” half of the nominal code 0 range, and continuing at 0 as the lower saturation limit, just like the full scale limit does. When you look at a bipolar ADC transfer function, it’s more obvious because the 0 voltage 0 LSB code point is in the center, with positive and negative full scale staircases in opposite directions. This unipolar ADC transfer function graph just looks weird because of where they stopped the horizontal axis.

share|improve this answer

answered 6 hours ago

MarkUMarkU

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$endgroup$

share|improve this answer

answered 6 hours ago

MarkUMarkU

7,54411 gold badge1313 silver badges2424 bronze badges

answered 6 hours ago

MarkUMarkU

7,54411 gold badge1313 silver badges2424 bronze badges

answered 6 hours ago

MarkUMarkU

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0

$begingroup$

A typical ADC gets very, very nonlinear as you hit the saturation. The 1/2 LSB is just the tip of it, since it reads 0 for any voltage below 0. It’s all kind of theoretical anyway since most ADCs have more than 1/2 LSB of offset voltage.

share|improve this answer

answered 2 hours ago

Spehro PefhanySpehro Pefhany

225k55 gold badges180180 silver badges473473 bronze badges

$endgroup$

add a comment
 | 

0

$begingroup$

A typical ADC gets very, very nonlinear as you hit the saturation. The 1/2 LSB is just the tip of it, since it reads 0 for any voltage below 0. It’s all kind of theoretical anyway since most ADCs have more than 1/2 LSB of offset voltage.

share|improve this answer

answered 2 hours ago

Spehro PefhanySpehro Pefhany

225k55 gold badges180180 silver badges473473 bronze badges

$endgroup$

add a comment
 | 

$begingroup$

A typical ADC gets very, very nonlinear as you hit the saturation. The 1/2 LSB is just the tip of it, since it reads 0 for any voltage below 0. It’s all kind of theoretical anyway since most ADCs have more than 1/2 LSB of offset voltage.

share|improve this answer

answered 2 hours ago

Spehro PefhanySpehro Pefhany

225k55 gold badges180180 silver badges473473 bronze badges

$endgroup$

share|improve this answer

answered 2 hours ago

Spehro PefhanySpehro Pefhany

225k55 gold badges180180 silver badges473473 bronze badges

answered 2 hours ago

Spehro PefhanySpehro Pefhany

225k55 gold badges180180 silver badges473473 bronze badges

answered 2 hours ago

Spehro PefhanySpehro Pefhany

225k55 gold badges180180 silver badges473473 bronze badges